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8 Mbit 1.8V SPI Serial Flash
A Microchip Technology Company
SST25WF080
Not Recommended for New Designs
Read-Status-Register (RDSR)
The Read-Status-Register (RDSR) instruction, 05H, allows reading of the status register. The status
register may be read at any time even during a Write (Program/Erase) operation. When a Write opera-
tion is in progress, the Busy bit may be checked before sending any new commands to assure that the
new commands are properly received by the device. CE# must be driven low before the RDSR instruc-
tion is entered and remain low until the status data is read. Read-Status-Register is continuous with
ongoing clock cycles until it is terminated by a low to high transition of the CE#. See Figure 18 for the
RDSR instruction sequence.
CE#
MODE 3
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SCK
SI
MODE 0
MSB
05
SO
HIGH IMPEDANCE
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB
Status
Register Out
1203 F17.0
Figure 18: Read-Status-Register (RDSR) Sequence
Write-Enable (WREN)
The Write-Enable (WREN) instruction, 06H, sets the Write-Enable-Latch bit in the Status Register to 1
allowing Write operations to occur. The WREN instruction must be executed prior to any Write (Pro-
gram/Erase) operation. The WREN instruction may also be used to allow execution of the Write-Sta-
tus-Register (WRSR) instruction; however, the Write-Enable-Latch bit in the Status Register will be
cleared upon the rising edge CE# of the WRSR instruction. CE# must be driven high before the WREN
instruction is executed. See Figure 19 for the WREN instruction sequence.
CE#
MODE 3
0 1 2 3 4 5 6 7
SCK
SI
SO
MODE 0
06
MSB
HIGH IMPEDANCE
1203 F18.0
Figure 19: Write Enable (WREN) Sequence
?2012 Silicon Storage Technology, Inc.
20
DS25024B
03/12
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